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ltc3869/ltc3869-2 1 38692fa for more information www.linear.com/ltc3869 typical a pplica t ion descrip t ion dual, 2-phase synchronous step-down dc/dc controllers the lt c ? 3869 is a high performance dual synchronous step-down switching regulator controller that drives all n- channel synchronous power mosfet stages. a constant frequency current mode architecture allows a phase- lockable frequency of up to 780 khz. power loss and noise due to the esr of the input capacitors are minimized by operating the two controller output stages out-of-phase. opti-loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. a wide 4 v to 38 v input supply range encompasses most battery chemistries. independent tk/ ss pins for each controller ramp the output voltage during start-up. current foldback limits mosfet heat dissipation during short-circuit conditions. the mode/pllin pin selects among burst mode ? operation, pulse-skipping mode, or continuous inductor current mode and allows the ic to be synchronized to an external clock. the ltc3869 is available in a 4 mm 5 mm qfn package and the ltc3869-2 is available in an ssop-28 package. the ltc3869 is pin-compatible with the ltc3850. l , lt , lt c , lt m , linear technology, the linear logo, opti - loop, burst mode and polyphase are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s . patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6580258, 6498466, 6611131. fea t ures a pplica t ions n dual, 180 phased controllers reduce required input capacitance and power supply induced noise n accurate multiphase current matching n r sense or dcr current sensing n 0.75% 0.6v output v oltage accuracy n phase-lockable fixed frequency 250khz to 780khz n high efficiency: up to 95% n dual n-channel mosfet synchronous drive n wide v in range: 4v to 38v (40v max) operation n wide v out range: 0.6v to 12.5v operation n adjustable soft-start current ramping or tracking n foldback output current limiting n output overvoltage protection n power good output voltage monitor n 5v low dropout regulator n small 28-lead qfn and narrow ssop packages n server systems n telecom systems n industrial and medical instruments n high power battery-operated devices n dc power distribution systems high efficiency dual 5v/3.3v step-down converter efficiency and power loss load current (a) 0.01 efficiency (%) power loss (mw) 100 10 90 70 50 30 80 60 40 20 0 1300 500 1000 1100 1200 400 700 600 3869 ta01b 10 1 0.1 efficiency power loss 900 800 v in = 12v, v out = 3.3v v in = 12v, v out = 5v 0.1f 147k 3.2h 470pf f in 500khz 1f 22f 47f 20k 15k v out1 5v 5a 0.1f 2.2h 470pf 56f 20k 15k 122k v out2 3.3v 5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 pgnd freq sense1 + sense2 + run2 run1 sense1 ? sense2 ? v fb1 v fb2 i th1 i th2 v in intv cc tk/ss1 tk/ss2 v in 7v to 24v 3869 ta01 sgnd pgood 0.1f 0.1f ltc3869 mode/pllin i lim 4.7f + + + 90.9k
ltc3869/ltc3869-2 2 38692fa for more information www.linear.com/ltc3869 a bsolu t e maxi m u m r a t ings (note 1) p in c on f igura t ion o r d er i n f or m a t ion input supply voltage : v in ........................... 40 v to C0.3 v top side driver voltages : boost 1, boost2 ...................................... 46 v to C0.3 v switch voltage : sw 1, sw2 ........................... 40 v to C5 v intv cc , run 1, run 2, pgood , extv cc , boost 1- sw 1, boost 2- sw2 ....................... 6 v to C0.3 v sense 1 + , sense 2 + , sense 1 C , sense 2 C voltages ...................................... 13 v to C0.3 v mode / pllin , i lim , tk / ss 1, tk / ss 2, freq voltages ...................................... int v cc to C0.3 v i th 1 , i th 2 , v fb 1 , v fb 2 voltages ............. in tv cc to C0.3 v intv cc peak output current ................................ 10 0 ma operating junction temperature range ( note 2) .................................................. C 4 0 c to 125 c junction temperature ( note 3) ............................. 12 5 c storage temperature range .................. C 6 5 c to 150 c lead temperature ( soldering , 10 sec ) gn package ...................................................... 30 0 c 9 10 top view sgnd 29 ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 sense1 ? tk/ss1 i th1 v fb1 v fb2 i th2 tk/ss2 sense2 ? boost1 bg1 v in intv cc bg2 pgnd boost2 tg2 sense1 + run1 freq mode/pllin sw1 tg1 sense2 + run2 i lim extv cc pgood sw2 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 34c/w, exposed pad (pin 29) is sgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run1 sense1 + sense1 ? v fb1 tk/ss1 i th1 sgnd i th2 tk/ss2 v fb2 sense2 ? sense2 + run2 extv cc freq mode/pllin sw1 tg1 boost1 bg1 v in intv cc bg2 pgnd boost2 tg2 sw2 pgood t jmax = 125c, ja = 80c/w lead free finish tape and reel part marking* package description temperature range ltc3869eufd#pbf ltc3869eufd#trpbf 3869 28-lead (4mm 5mm) plastic qfn C40c to 125c ltc3869iufd#pbf ltc3869iufd#trpbf 3869 28-lead (4mm 5mm) plastic qfn C40c to 125c ltc3869ign-2#pbf ltc3869ign-2#trpbf ltc3869gn-2 28-lead narrow plastic ssop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc3869/ltc3869-2 3 38692fa for more information www.linear.com/ltc3869 symbol parameter conditions min typ max units main control loops v in input voltage range 4 38 v v out output voltage range 0.6 12.5 v v fb1,2 regulated feedback voltage (notes 2, 4) i th1,2 voltage = 1.2v, 0c to 85c i th1,2 voltage = 1.2v, C40c to 125c l l 0.5955 0.5940 0.600 0.600 0.6045 0.6060 v v i fb1,2 feedback current (note 4) C15 C50 na v reflnreg reference voltage line regulation v in = 4.0v to 38v (note 4) 0.002 0.01 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; ?i th voltage = 1.2v to 0.7v measured in servo loop; ?i th voltage = 1.2v to 1.6v l l 0.01 C0.01 0.1 C0.1 % % g m1,2 transconductance amplifier g m i th1,2 = 1.2v; sink/source 5a; (note 4) 2 mmho i q input dc supply current normal mode shutdown (note 5) v in = 15v v run1,2 = 0v 3 30 50 ma a df max maximum duty factor in dropout 94 95 % uvlo undervoltage lockout v intvcc ramping down l 3.0 3.2 3.4 v uvlo hys uvlo hysteresis 0.6 v v ovl feedback overvoltage lockout measured at v fb1,2 l 0.64 0.66 0.68 v i sense sense pins bias current (each channel); v sense1,2 = 3.3v l 1 2 a i tk/ss1,2 soft-start charge current v tk/ss1,2 = 0v l 1.0 1.25 1.5 a v run1,2 run pin on threshold v run1 , v run2 rising l 1.1 1.22 1.35 v v run 1, 2(hys) run pin on hysteresis 80 mv v sense(max) maximum current sense threshold, 0c to 85c (note 2) v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = 0v v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = float v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = intv cc l l l 25 45 68 30 50 75 35 55 82 mv mv mv maximum current sense threshold, C40c to 125c (note 2) v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = 0v v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = float v fb1,2 = 0.5v, v sense1,2 = 3.3v, i lim = intv cc v fb1,2 = 0.5v, v sense1,2 = 3.3v, ltc3869ign-2 l l l l 23 43 68 40 30 50 75 50 37 57 82 60 mv mv mv mv v mismatch channel to channel current sense mismatch voltage of v sense(max) i lim = float 2 mv tg1, 2 t r tg1, 2 t f tg transition time: rise t ime fall t ime (note 8) c load = 3300pf c load = 3300pf 25 25 ns ns bg1, 2 t r bg1, 2 t f bg transition time: rise t ime fall t ime (note 8) c load = 3300pf c load = 3300pf 25 25 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver (note 6) 30 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver (note 6) 30 ns t on(min) minimum on-time (note 7) 90 ns e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run1,2 = 5v unless otherwise noted.
ltc3869/ltc3869-2 4 38692fa for more information www.linear.com/ltc3869 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3869 is tested under pulsed load conditions such that t j t a . the ltc3869e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3869i is guaranteed to meet performance specifications over the full C40c to 125c operating junction temperature range. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run1,2 = 5v unless otherwise noted. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc3869ufd: t j = t a + (p d ? 34c/w) ltc3869gn-2: t j = t a + (p d ? 80c/w) note 4: the ltc3869 is tested in a feedback loop that servos v ith1,2 to a specified voltage and measures the resultant v fb1,2 . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: delay times are measured using 50% levels. note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 8: guaranteed by design. symbol parameter conditions min typ max units intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 38v 4.8 5 5.2 v v ldo int intv cc load regulation i cc = 0ma to 20ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive l 4.5 4.7 v v ldohys extv cc hysteresis 200 mv v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 50 100 mv pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 2 a v pg pgood trip level v fb with respect to set output voltage v fb ramping negative v fb ramping positive C10 10 % % oscillator and phase-locked loop f nom nominal frequency v freq = 1.2v 450 500 550 khz f low lowest frequency v freq = 0v 210 250 290 khz f high highest frequency v freq 2.4v 700 780 850 khz r mode/pllin mode/pllin input resistance 250 k? i freq frequency setting current 9 10 11 a on chip driver tg r up tg pull-up r ds(on) tg high 2.6 tg r down tg pull-down r ds(on) tg low 1.5 bg r up bg pull-up r ds(on) bg high 2.4 bg r down bg pull-down r ds(on) bg low 1.1
ltc3869/ltc3869-2 5 38692fa for more information www.linear.com/ltc3869 efficiency vs output current and mode efficiency vs output current and mode full load efficiency and power loss vs input voltage load current (a) 0.01 efficiency (%) 100 10 90 70 50 30 80 60 40 20 0 10 3869 g01 100 1 0.1 v in = 12v v out = 1.8v burst mode operation dcm ccm circuit of figure 16 load current (a) 0.01 efficiency (%) 100 10 90 70 50 30 80 60 40 20 0 10 3869 g02 100 1 0.1 v in = 12v v out = 1.2v burst mode operation dcm ccm circuit of figure 16 input voltage (v) 5 75 efficiency (%) 80 85 90 2 power loss (w) 3 4 5 10 20 15 3869 g03 1.8v 1.8v 1.2v 1.2v efficiency power loss circuit of figure 16 typical p er f or m ance c harac t eris t ics load step (burst mode operation) load step (forced continuous mode) load step (pulse-skipping mode) inductor current at light load prebiased output at 2v t a = 25c, unless otherwise noted. v in = 12v v out = 1.8v i load = 400ma 1s/div 3869 g07 forced continuous mode 5a/div burst mode operation 5a/div pulse- skipping mode 5a/div v in = 12v v out = 3.3v 2ms/div 3869 g08 tk/ss 500mv/div v fb 500mv/div v out 2v/div v in = 12v v out = 1.8v 50s/div 3869 g04 i l 5a/div v out 100mv/div ac-coupled i load 5a/div 300ma to 5a v in = 12v v out = 1.8v 50s/div 3869 g05 i l 5a/div v out 100mv/div ac-coupled i load 5a/div 300ma to 5a v in = 12v v out = 1.8v 50s/div 3869 g06 i l 5a/div v out 100mv/div ac-coupled i load 5a/div 300ma to 5a
ltc3869/ltc3869-2 6 38692fa for more information www.linear.com/ltc3869 typical p er f or m ance c harac t eris t ics current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage maximum current sense threshold vs duty cycle maximum current sense voltage vs feedback voltage (current foldback) tracking up and down with external ramp quiescent current without extv cc vs temperature intv cc line regulation v in = 12v v out1 = 1.8v, 1.5 load v out2 = 1.2v, 1 load 10ms/div 3869 g10 tk/ss1 tk/ss2 2v/div v out1 v out2 500ma/div v out1 v out2 intv cc voltage (v) 5.5 5.0 4.5 4.0 3.0 3.5 2.5 2.0 input voltage (v) 0 10 30 3869 g12 40 20 v ith (v) 0 ?40 v sense (mv) ?20 0 20 40 60 80 0.5 1 1.5 2 3869 g13 i lim = gnd i lim = float i lim = intv cc v sense common mode voltage (v) 0 current sense threshold (mv) 30 40 50 12 20 10 0 2 6 8 10 4 60 70 80 3869 g14 i lim = gnd i lim = float i lim = intv cc 60 80 40 20 50 70 30 10 0 duty cycle (%) 0 current sense threshold (mv) 60 100 20 40 80 3869 g15 i lim = gnd i lim = float i lim = intv cc feedback voltage (v) 0 maximum current sense threshold (mv) 30 40 50 0.6 20 10 0 0.1 0.3 0.4 0.5 0.2 60 70 90 80 3869 g16 i lim = gnd i lim = float i lim = intv cc t a = 25c, unless otherwise noted. quiescent current (ma) 4.0 3.0 2.0 1.0 3.5 2.5 1.5 0.5 0 temperature (c) ?50 50 0 100 3869 g11 125 25 ?25 75 coincident tracking 5ms/div 3869 g09 run 2v/div v out1 v out2 1v/div v out1 v out2 v out1 = 1.8v, 1.5 load v out2 = 1.2v, 1 load
ltc3869/ltc3869-2 7 38692fa for more information www.linear.com/ltc3869 tk/ss pull-up current vs temperature tk/ss current (a) 1.6 1.2 1.4 1.0 temperature (c) ?50 50 0 100 3869 g17 125 25 ?25 75 typical p er f or m ance c harac t eris t ics undervoltage lockout threshold (intv cc ) vs temperature oscillator frequency vs input voltage shutdown (run) threshold vs temperature regulated feedback voltage vs temperature oscillator frequency vs temperature temperature (c) ?50 900 800 700 500 600 0 100 200 300 400 25 75 3869 g20 ?25 0 50 125100 frequency (khz) v freq = gnd v freq = 1.2v v freq = intv cc temperature (c) ?40 4.1 3.9 2.9 3.7 2.7 3.1 3.5 2.5 3.3 20 60 3869 g21 ?20 0 40 10080 uvlo threshold (v) falling rising input voltage (v) 5 520 510 500 490 480 25 35 3869 g22 10 15 20 40 30 frequency (khz) t a = 25c, unless otherwise noted. temperature (c) ?50 1.24 1.22 1.20 1.18 1.12 1.16 1.14 1.10 1.08 25 75 3869 g18 ?25 0 50 125100 run pin threshold (v) off on temperature (c) ?40 604 602 600 598 590 592 594 596 35 85 3869 g19 ?15 10 60 125110 regulated feedback voltage (mv)
ltc3869/ltc3869-2 8 38692fa for more information www.linear.com/ltc3869 p in func t ions run1, run 2 (pin 27, pin 10/pin 1, pin 13): run control inputs. a voltage above 1.2 v on either pin turns on the ic. however, forcing either of these pins below 1.2 v causes the ic to shut down the circuitry required for that particular channel. there are 1 a pull-up currents for these pins. once the run pin raises above 1.2 v, an additional 4.5a pull-up current is added to the pin. v fb1 , v fb2 (pin 4, pin 5/pin 4, pin 10): error amplifier feedback inputs. these pins receive the remotely sensed feedback voltages for each channel from external resistive dividers across the outputs. i th1 , i th2 (pin 3, pin 6/pin 6, pin 8): current control thresholds and error amplifier compensation points. each associated channels current comparator tripping threshold increases with its i th control voltage. sgnd (pin 29/pin 7): signal ground. all small-signal components and compensation components should con- nect to this ground, which in turn connects to pgnd at one point. pin 29 is the exposed pad, only available for the ufd package. the exposed pad must be soldered to pcb ground for electrical connection and rated thermal performance. tk/ss1, tk/ss 2 (pin 2, pin 7 /pin 5, pin 9): output volt- age tracking and soft-start inputs. when one particular channel is configured to be the master of two channels, a capacitor to ground at this pin sets the ramp rate for the master channels output voltage. when the channel is configured to be the slave of two channels, the v fb voltage of the master channel is reproduced by a resistor divider and applied to this pin. internal soft-start currents of 1.2a are charging these pins. mode/pllin (pin 25/pin 27): forced continuous mode, burst mode operation, or pulse-skipping mode selection pin and external synchronization input to phase detec- tor pin. connect this pin to sgnd to force both channels in continuous mode of operation. connect to intv cc to enable pulse-skipping mode of operation. leave the pin floating will enable burst mode operation. a clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator with the clock on this pin. the pll compensation components are integrated inside the ic. (ufd/gn) shutdown current vs input voltage shutdown current vs temperature quiescent current vs input voltage without extv cc input voltage (v) 5 60 50 40 30 20 10 0 25 35 3869 g23 10 15 20 40 30 shutdown input current (a) input voltage (v) 5 3.8 3.6 3.4 2.6 2.4 1.8 2.0 2.2 2.8 3.0 3.2 25 35 3869 g25 10 15 20 40 30 supply current (ma) 45 40 35 30 20 10 25 15 5 0 3869 g24 shutdown current (a) temperature (c) ?50 25 75 ?25 0 50 125100 typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted.
ltc3869/ltc3869-2 9 38692fa for more information www.linear.com/ltc3869 p in func t ions (ufd/gn) freq (pin 26/pin 28): there is a precision 10 a current flowing out of this pin. connect a resistor to ground set the controllers operating frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. i lim ( pin 11/na): current comparator sense voltage range inputs. this pin is to be programmed to sgnd, float or intv cc to set the maximum current sense threshold to three different levels for each comparator. the current limit default value is set to be 50mv for ltc3869gn-2. extv cc (pin 12/pin 14): external power input to an inter- nal switch connected to intv cc . this switch closes and supplies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7 v. do not exceed 6v on this pin. v in (pin 20/pin 22): main input supply. decouple this pin to pgnd with a capacitor (0.1f to 1f). boost1, boost 2 (pin 22, pin 16/pin 24, pin 18): boosted floating driver supplies. the (+) terminal of the booststrap capacitors connect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . tg1, tg 2 (pin 23, pin 15/pin 25, pin 17): top gate driver outputs . these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch nodes voltages. sw1, sw 2 (pin 24, pin 14/pin 26, pin 16): switch node connections to inductors. voltage swing at these pins is from a schottky diode ( external) voltage drop below ground to v in . sense1 + , sense2 + (pin 28, pin 9/pin 2, pin 12): current sense comparator inputs. the (+) inputs to the current comparators are normally connected to dcr sensing networks or current sensing resistors. sense1 C , sense2 C ( pin 1, pin 8/pin 3, pin 11): current sense comparator inputs. the (C) inputs to the current comparators are connected to the outputs. pgnd (pin 17/pin 19): power ground pin. connect this pin closely to the sources of the bottom n-channel mos- fets, the (C) terminal of cv cc and the (C) terminal of c in . bg1, bg 2 (pin 21, pin 18/pin 23, pin 20): bottom gate driver outputs. these pins drive the gates of the bottom n-channel mosfets between pgnd and intv cc . intv cc (pin 19/pin 21): internal 5 v regulator output. the control circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 4.7 f low esr tan- talum or ceramic capacitor. pgood (pin 13/pin 15): power good indicator output. open drain logic out that is pulled to ground when either channel output exceeds 10% regulation windows, after the internal 20s power bad mask timer expires.
ltc3869/ltc3869-2 10 38692fa for more information www.linear.com/ltc3869 func t ional b lock diagra m 4.7v ? + + ? ? + v in 1 a slope compensation uvlo ltc3869ufd only slope recovery active clamp osc s rq 3k run switch logic and anti- shoot through bg on fcnt 0.6v ov 1.2v 0.5v i th r c intv cc intv cc i lim i cmp c c1 ss sgnd r1 0.66v r2 run pgnd pgood intv cc extv cc i rev sw tg c b v in c in v in sleep boost bursten ? + ? + uv ov c vcc v out c out m2 m1 l1 d b mode/pllin sense + sense ? ? + 0.6v ref tk/ss run 0.5v + ? v fb freq pll-sync mode/sync detect + 5v reg 1.2 a c ss + ? + ? + f f 0.54v 3869 fd 1 51k i thb ? + ea + 10a
ltc3869/ltc3869-2 11 38692fa for more information www.linear.com/ltc3869 o pera t ion main control loop the ltc3869 is a constant-frequency, current mode step- down controller with two channels operating 180 degrees out-of-phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of each error ampli- fier ea. the v fb pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight decrease in v fb relative to the 0.6 v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator i rev , or the beginning of the next cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the int v cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7 v, an internal 5 v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7 v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source such as one of the ltc3869 switching regulator outputs. each top mosfet driver is biased from the floating bootstrap capacitor c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100ns every third cycle to allow c b to recharge. however, it is recommended that a load be present or the ic operates at low frequency during the drop-out transition to ensure c b is recharged. shutdown and start-up (run1, run2 and tk/ss1, tk /ss2 pins) the two channels of the ltc3869 can be independently shut down using the run1 and run2 pins. pulling either of these pins below 1.2 v shuts down the main control loop for that controller. pulling both pins low disables both controllers and most internal circuits, including the intv cc regulator. releasing either run pin allows an internal 1 a current to pull up the pin and enable that controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of each controllers output voltage v out is controlled by the voltage on the tk/ss1 and tk/ss2 pins. when the voltage on the tk/ss pin is less than the 0.6v internal reference, the ltc3869 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.6 v reference. this allows the tk/ss pin to be used to program the soft-start period by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.2 a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin . as the tk/ss voltage rises linearly from 0 v to 0.6v (and beyond), the output voltage v out rises smoothly from zero to its final value. alternatively the tk/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other supply to ground ( see the applications information section). when the corresponding run pin is pulled low to disable a controller, or when intv cc drops below its undervoltage lockout threshold of 3.2 v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, both controllers are disabled and the external mosfets are held off.
ltc3869/ltc3869-2 12 38692fa for more information www.linear.com/ltc3869 light load current operation (burst mode operation, pulse-skipping, or continuous conduction) the ltc3869 can be enabled to enter high efficiency burst mode operation, constant - frequency pulse- skipping mode, or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to a dc voltage below 0.6 v ( e.g., sgnd). to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. when a controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.5 v, the internal sleep signal goes high ( enabling sleep mode) and the top mosfet is turned off immediately, but the bottom mosfet is turned off when the inductor current reaches zero. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the ea s output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller oper- ates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the ltc3869 operates in pwm pulse-skipping mode at light loads. at very light loads, the current comparator i cmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles ( i.e., skipping pulses). the inductor current is not allowed to reverse ( discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. single output multiphase operation the ltc3869 can be used for single output multiphase converters by making these connections ? tie all of the i th pins together. ? tie all of the v fb pins together. ? tie all of the tk/ss pins together. ? tie all of the run pins together. ltc3869 has excellent current matching performance between channels to ensure that there are equal thermal stress for both channels. frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to main- tain low output ripple voltage. the switching frequency of the ltc3869 controller can be selected using the freq pin. if the mode/pllin pin is not being driven by an external clock source, the freq pin can be used to program the controllers operating frequency from 250 khz to 780khz. there is a precision 10 a current flowing out of the freq pin, so the user can program the controllers switch- ing frequency with a single resistor to sgnd. a curve is provided later in the application section showing the relationship between the voltage on the freq pin and switching frequency. a phase-locked loop (pll) is integrated on the ltc3869 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller is operating in forced continuous mode when it is synchronized. o pera t ion
ltc3869/ltc3869-2 13 38692fa for more information www.linear.com/ltc3869 the pll loop filter network is integrated inside the ltc3869. the phase-locked loop is capable of locking any frequency within the range of 250 khz to 780 khz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. power good (pgood pin) when v fb pin voltage is not within 10% of the 0.6v reference voltage, the pgood pin is pulled low. the pgood pin is also pulled low when the run pin is below 1.2v or when the ltc3869 is in the soft-start or tracking phase. the pgood pin will flag power good immediately when both v fb pins are within the 10% of the reference window. however, there is an internal 20 s power bad mask when v fb goes out the 10% window. the pgood pin is allowed to be pulled up by an external resistor to a source of up to 6v. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. o pera t ion
ltc3869/ltc3869-2 14 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion the typical application on the first page is a basic ltc3869 application circuit. ltc3869 can be configured to use either dcr ( inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resis- tors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load require- ment, and begins with the selection of r sense ( if r sense is used) and inductor value. next, the power mosfets are selected. finally, input and output capacitors are selected. current limit programming the i lim pin is a tri-level logic input which sets the maxi- mum current limit of the controller. when i lim is either grounded, floated or tied to intv cc , the typical value for the maximum current sense threshold will be 30mv, 50mv or 75mv, respectively. which setting should be used? for the best current limit accuracy, use the 75 mv setting. the 30 mv setting will allow for the use of very low dcr inductors or sense resistors, but at the expense of current limit accuracy. the 50 mv setting is a good balance between the two. for single output dual phase applications, use the 50 mv or 75mv setting for optimal current sharing. sense + and sense C pins the sense + and sense C pins are the inputs to the current comparators. the common mode input voltage range of the current comparators is 0 v to 12.5 v. both sense pins are high impedance inputs with small base currents of less than 1 a. when the sense pins ramp up from 0 v to 1.4v, the small base currents flow out of the sense pins. when the sense pins ramp down from 12.5 v to 1.1 v, the small base currents flow into the sense pins. the high imped- ance inputs to the current comparators allow accurate dcr sensing. however, care must be taken not to float these pins during normal operation. the ltc3869gn-2 defaults to 50mv current limit value. filter components mutual to the sense lines should be placed close to the ltc3869, and the sense lines should run close together to a kelvin connection underneath the current sense element ( shown in figure 1). sensing cur- rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2 b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. figure 1. sense lines placement with sense resistor c out to sense filter, next to the controller r sense 3869 f01 low value resistors current sensing a typical sensing circuit using a discrete resistor is shown in figure 2 a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the input common mode range of the current comparator is 0 v to 12.5v. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to- peak ripple current , ? i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ?i l 2 because of possible pcb noise in the current sensing loop, the ac current sensing ripple of ?v sense = ?i l ? r sense also needs to be checked in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, a 10mv ?v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications, for duty cycles less than 40%.
ltc3869/ltc3869-2 15 38692fa for more information www.linear.com/ltc3869 for previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75 mv for the ltc1628 / ltc3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. for todays highest current density solutions, however, the value of the sense resistor can be less than 1 m? and the peak sense voltage can be as low as 20 mv. in addition, inductor ripple currents greater than 50% with operation up to 1 mhz are becoming more com- mon. under these conditions the voltage drop across the sense resistor s parasitic inductance is no longer negligible. a typical sensing circuit using a discrete resistor is shown in figure 2 a. in previous generations of controllers, a small rc filter placed near the ic was commonly used to reduce the effects of capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 10? resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 20ns. this same rc filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. for example, figure 3 illustrates the voltage waveform across a 2 m? sense resistor with a 2010 footprint for the 1.2v /15 a converter operating at 100% load. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl = v esl(step) ?i l t on ? t off t on + t off a pplica t ions i n f or m a t ion figure 2. tw o different methods of sensing current (2a) using a resistor to sense current (2b) using the inductor dcr to sense current v in v in intv cc boost tg sw bg pgnd filter components placed near sense pins sense + sense ? sgnd ltc3869 v out 3869 f02a c f ? 2 rf esl/r s pole-zero cancellation sense resistor plus parasitic inductance r s esl c f r f r f v in v in intv cc boost tg sw bg pgnd *place c1 near sense + , sense ? pins **place r1 next to inductor inductor dcrl sense + sense ? sgnd ltc3869 v out 3869 f02b r1** r2c1* r1 || r2 c1 = l dcr r sense(eq) = dcr r2 r1 + r2
ltc3869/ltc3869-2 16 38692fa for more information www.linear.com/ltc3869 if the rc time constant is chosen to be close to the parasitic inductance divided by the sense resistor ( l/r), the resulting waveform looks resistive again, as shown in figure 4. for applications using low maximum sense voltages, check the sense resistor manufacturer s data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use the equation above to determine the esl. however, do not over- filter. keep the rc time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on v rsense . the above generally applies to high density/high current applications where i max >10 a and low values of inductors are used. for applications where i max <10 a, set r f to 10? and c f to 1000 pf. this will provide a good starting point. a pplica t ions i n f or m a t ion figure 3. voltage waveform measured directly across the sense resistor figure 4. voltage waveform measured after the sense resistor filter. c f = 1000pf, r f = 100? 500ns/div v sense 20mv/div 3869 f03 v esl(step) 500ns/div v sense 20mv/div 3869 f04 the filter components need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair and kelvin connected to the sense resistor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc3869 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2 b. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1 m? for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to dcr sensing . if the external r1 || r 2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r 2/(r 1 + r 2). r 2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + ?i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense( max) ) in the electrical characteristics table (23mv, 43mv, or 68mv, depending on the state of the i lim pin). next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c.
ltc3869/ltc3869-2 17 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r sense(equiv) dcr (max) at t l(max) c1 is usually selected to be in the range of 0.047 f to 0.47f. this forces r1 || r2 to around 2 k?, reducing er- ror that might have been caused by the sense pins 1a current. t l(max) is the maximum inductor temperature. the equivalent resistance r1 || r2 is scaled to the room temperature inductance and maximum dcr: r1|| r2 = l (dcr at 20 c) ? c1 the sense resistor values are: r1 = r1|| r2 r d ; r2 = r1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. to maintain a good signal to noise ratio for the current sense signal, use a minimum ? v sense of 10 mv for duty cycles less than 40%. for a dcr sensing application, the actual ripple voltage will be determined by the equation: ?v sense = v in ? v out r1 ? c1 v out v in ? f osc slope compensation and inductor peak current slope compensation provides stability in constant- frequency architectures by preventing subharmonic oscil- lations at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. however, the ltc3869 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency f osc directly determine the inductors peak-to-peak ripple current: i ripple = v out v in v in C v out f osc ? l ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) for a duty cycle less than 40%. note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v in C v out f osc ? i ripple ? v out v in for duty cycles greater than 40%, the 10 mv current sense ripple voltage requirement is relaxed because the slope compensation signal aids the signal-to-noise ratio and because a lower limit is placed on the inductor value to avoid subharmonic oscillations. to ensure stability for
ltc3869/ltc3869-2 18 38692fa for more information www.linear.com/ltc3869 duty cycles up to the maximum of 95%, use the following equation to find the minimum inductance. l min > v out f sw ? i load(max) ? 1.4 where l min is in units of h f sw is in units of mhz inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection tw o external power mosfets must be selected for each controller in the ltc3869: one n-channel mosfet for the top ( main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5 v during start- up ( see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5 v); then, sub-logic level threshold mosfets (v gs(th) < 3 v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in C v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i max ( ) 2 1 + d ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc C v th(min) + 1 v th(min) ? ? ? ? ? ? ? ? 2 ? f osc p sync = v in C v out v in i max ( ) 2 1 + d ( ) r ds(on) where d is the temperature dependency of r ds(on) and r dr (approximately 2?) is the effective driver resistance at the mosfets miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n- channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20 v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input a pplica t ions i n f or m a t ion
ltc3869/ltc3869-2 19 38692fa for more information www.linear.com/ltc3869 voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. the optional schottky diodes conduct during the dead time between the conduction of the two power mosfets. these prevent the body diodes of the bottom mosfets from turn- ing on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1 a to 3 a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. a schottky diode in parallel with the bottom fet may also provide a modest improvement in burst mode efficiency. soft-start and tracking the ltc3869 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when one particular channel is configured to soft-start by itself, a capacitor should be connected to its tk/ss pin. this channel is in the shutdown state if its run pin voltage is below 1.2 v. its tk/ss pin is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.2 v, the channel pow- ers up. a soft-start current of 1.2 a then starts to charge its soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0 v to 0.6 v on the tk/ss pin. the total soft-start time can be calculated as: t softstart = 0.6 ? c ss 1.2a regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse-skipping mode up to tk/ss = 0.5 v. between tk/ss = 0.5 v and 0.54 v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.54 v. the output ripple is minimized during the 40 mv forced continuous mode window ensuring a clean pgood signal. when the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. there- fore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft-start capacitor charging current is always flowing, producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the ltc3869 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.54 v regardless of the setting on the mode/pllin pin. however, the ltc3869 should always be set in force continuous mode tracking down when there is no load. after tk/ss drops below 0.1 v, its channel will operate in discontinuous mode. a pplica t ions i n f or m a t ion
ltc3869/ltc3869-2 20 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion output voltage tracking the ltc3869 allows the user to program how its output ramps up and down by means of the tk/ss pins. through these pins, the output can be set up to either coincidentally or ratiometrically track another supplys output, as shown in figure 5. in the following discussions, v out1 refers to the ltc3869s output 1 as a master channel and v out2 refers to the ltc3869s output 2 as a slave channel. in practice, though, either phase can be used as the master. to implement the coincident tracking in figure 5 a, con- nect an additional resistive divider to v out1 and connect its midpoint to the tk/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 6 a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 6 b, the ratio of the v out2 divider should be exactly the same as the master channels feedback divider shown in figure 6b. by selecting different resistors, the ltc3869 can achieve different modes of tracking including the two in figure 5. so which mode should be programmed? while either mode in figure 5 satisfies most practical applications, some trade-offs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. when the master channels output experiences dynamic excursion ( under load transient, for example), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. figure 5. tw o different modes of output voltage tracking figure 6. setup for coincident and ratiometric tracking time (5a) coincident tracking v out1 v out2 output voltage 3869 f05a v out1 v out2 time 3869 f08b (5b) ratiometric tracking output voltage r3 r1 r4 r2 r3 v out2 r4 (6a) coincident tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3869 f09 (6b) ratiometric tracking setup to v fb1 pin to tk/ss2 pin to v fb2 pin v out1
ltc3869/ltc3869-2 21 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion intv cc regulators and extv cc the ltc3869 features a true pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the ltc3869s internal circuitry. the linear regulator regulates the voltage at the intv cc pin to 5 v when v in is greater than 5.5 v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7 v. each of these can supply a peak current of 100 ma and must be bypassed to ground with a minimum of 4.7 f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3869 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5 v linear regulator or extv cc . when the voltage on the extv cc pin is less than 4.7 v, the linear regulator is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the ltc3869 intv cc current is limited to less than 42 ma from a 38 v supply in the ufd package and not using the extv cc supply: t j = 70c + (42ma)(38v)(34c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode ( mode/ pllin = sgnd) at maximum v in . when the voltage applied to ext- v cc rises above 4.7 v, the intv cc linear regulator is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc remains above 4.5 v. using the extv cc allows the mosfet driver and control power to be derived from one of the ltc 3869s switching regulator outputs during normal operation and from the intv cc when the output is out of regulation (e.g., start-up, short-circuit). if more current is required through the extv cc than is specified, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6 v to the extv cc pin and make sure that extv cc < v in at all times. significant efficiency and thermal gains can be realized by powering intv cc from the output, since the v in cur- rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). tying the extv cc pin to a 5 v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (42ma)(5v)(34c/w) = 77c however, for 3.3 v and other low voltage outputs, additional circuitry is required to derive intv cc power from the output . the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open ( or grounded). this will cause intv cc to be powered from the internal 5 v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5 v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if a 5 v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output-derived boost net- work. for 3.3 v and other low voltage regulators , efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v.
ltc3869/ltc3869-2 22 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion for applications where the main input power is below 5v, tie the v in and intv cc pins together and tie the combined pins to the 5 v input with a 1? or 2.2? resistor as shown in figure 7 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic level devices. uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.2v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 600 mv of preci- sion hysteresis. another way to detect an undervoltage condition is to monitor the v in supply. because the run pins have a precision turn-on reference of 1.2 v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5 a of current flows out of the run pin once the run pin voltage passes 1.2 v. one can program the hysteresis of the run comparator by adjusting the values of the resistive divider. for accurate v in undervoltage detection, v in needs to be higher than 4.5v. c in and c out selection the selection of c in is simplified by the 2- phase architec- ture and its impact on the worst-case rms current drawn through the input network ( battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current oc- curs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output cur- rent drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/ 2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst- case condition is commonly used for design because even significant deviations do not of- fer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. figure 7. setup for a 5v input topside mosfet driver supply (c b , db) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mos- fets. capacitor c b in the functional diagram is charged though external diode db from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capa- citance of the topside mosfet (s). the reverse break- down of the external schottky diode must be greater than v in(max) . make sure the diode is a low leakage diode even at hot temperature to prevent leakage current feeding intv cc . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. undervoltage lockout the ltc3869 has two functions that help protect the controller in case of undervoltage conditions. a precision intv cc ltc3869 r vin 1 c in 3869 f07 4.7f 5v cintv cc + v in
ltc3869/ltc3869-2 23 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3869, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of the ltc3869 2- phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement cal- culated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2- phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply /battery is included in the efficiency testing. the sources of the top mosfets should be placed within 1 cm of each other and share a common c in (s). separating the sources and c in may pro- duce undesirable voltage and current resonances at v in . a small (0.1 f to 1 f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3869, is also suggested. a 2.2? to 10? resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance ( esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (?v out ) is approximated by: ?v out i ripple esr + 1 8fc out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. setting output voltage the ltc3869 output voltages are each set by an external feedback resistive divider carefully placed across the out- put, as shown in figure 8. the regulated output voltage is determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feed-forward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. figure 8. setting output voltage fault conditions: current limit and current foldback the ltc3869 includes current foldback to help limit load current when the output is shorted to ground. if the out- put falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one- third of the maximum value. foldback current limiting is disabled during the soft-start or tracking up. under short-circuit conditions with very low duty cycles, the ltc3869 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short- circuit ripple current is determined by the minimum on- time t on(min) of the ltc3869 ( 90 ns), the input voltage and inductor value: ?i l(sc) = t on(min) ? v in l the resulting short-circuit current is: i sc = 1/3 v sense(max) r sense C 1 2 ?i l(sc) 1/2 ltc3869 v fb v out r b c ff r a 3869 f08
ltc3869/ltc3869-2 24 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion phase-locked loop and frequency synchronization the ltc3869 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator (v co ) and a phase detector. this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the turn-on of controller 2 s top mosfet is thus 180 degrees out- of-phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. there is a precision 10 a of current flowing out of freq pin. this allows the user to use a single resistor to sgnd to set the switching frequency when no external clock is applied to the mode/ pllin pin. the internal switch between freq pin and the integrated pll filter network is on, allowing the filter network to be pre-charged to the same voltage potential as the freq pin. the relationship between the voltage on the freq pin and the operating frequency is shown in figure 9 and specified in the electri- cal characteristics table. if an external clock is detected on the mode/pllin pin, the internal switch mentioned above will turn off and isolate the influence of freq pin. note that the ltc3869 can only be synchronized to an external clock whose frequency is within range of the ltc3869s internal v co . this is guaranteed to be between 250 khz and 780khz. a simplified block diagram is shown in figure 10. if the external clock frequency is greater than the inter- nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the filter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the filter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. typically, the external clock ( on mode/ pllin pin ) input high threshold is 1.6 v, while the input low threshold is 1 v. it is not recommended to apply the external clock when ic is in shutdown. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the ltc3869 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t on(min) < v out v in (?) figure 9. relationship between oscillator frequency and voltage at the freq pin figure 10. phase-locked loop block diagram freq pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 3869 f09 2.5 0 100 300 400 500 900 800 700 200 600 digital phase/ frequency detector sync vco 2.4v 5v 10a r set 3869 f10 freq external oscillator mode/ pllin
ltc3869/ltc3869-2 25 38692fa for more information www.linear.com/ltc3869 if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3869 is approximately 90ns, with reasonably good pcb layout, minimum 40% inductor current ripple and at least 10mv C 15 mv ripple on the current sense signal. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time gradually increases to 130 ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l 3 + ...) where l1, l2, etc. are the individual losses as a per cent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3869 circuits : 1) ic v in current , 2) intv cc regulator current , 3) i 2 r losses , 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typi- cally results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur- rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through extv cc from an output- derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(efficiency). for example, in a 20 v to 5 v applica- tion, 10 ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more ( if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used), mosfet, inductor, current sense resistor. in continuous mode, the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to ob- tain i 2 r losses. for example, if each r ds(on) = 10m?, r l = 10m?, r sense = 5 m?, then the total resistance is 25 m?. this results in losses ranging from 2% to 8% as the output current increases from 3 a to 15 a for a 5 v output, or a 3% to 12% loss for a 3.3 v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15 v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss ? other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance a pplica t ions i n f or m a t ion
ltc3869/ltc3869-2 26 38692fa for more information www.linear.com/ltc3869 losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switch- ing frequency. a 25 w supply will typically require a minimum of 20 f to 40 f of capacitance having a maximum of 20 m? to 50 m? of esr. the ltc3869 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. modest improvements in burst mode efficiency may be realized by using a smaller inductor value, a lower switch- ing frequency or for dcr sensing applications, making the dcr filters time constant smaller than the l/dcr time constant for the inductor. a small schottky diode with a current rating equal to about 20% of the maximum load current or less may yield minor improvements, too. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load ( esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without break- ing the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be in- creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. a pplica t ions i n f or m a t ion
ltc3869/ltc3869-2 27 38692fa for more information www.linear.com/ltc3869 pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 11. figure 12 illustrates the current waveforms present in the various branches of the 2- phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets m1 and m3 located within 1 cm of each other with a common drain con- nection at c in ? do not attempt to split the input de- coupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter- minals. the v fb and i th traces should be as short as possible. the path formed by the top n-channel mos- fet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the ltc3869 v fb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense + and sense C leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1 f ceramic capacitor placed im- mediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes ( sw1, sw2), top gate nodes (tg1, tg2), and boost nodes ( boost1, boost2) away from sensitive small-signal nodes, especially from the opposite channels voltage and current sensing feed- back pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3869 and occupy minimum pc trace area. if dcr sensing is used, place the top resistor (figure 2b, r1) close to the switching node. 7. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node ( sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% of the maximum designed cur - rent level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb imple- mentation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. over- compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current com- parator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. a pplica t ions i n f or m a t ion
ltc3869/ltc3869-2 28 38692fa for more information www.linear.com/ltc3869 figure 11. recommended printed circuit layout diagram a pplica t ions i n f or m a t ion c b2 c b1 c intvcc + c in d1 1 f ceramic m1 m2 m3 m4 d2 + c vin v in r in l1 l2 c out1 v out1 gnd v out2 3869 f11 + c out2 + r sense r sense r pu2 pgood v pull-up f in 1 f ceramic i th1 v fb1 sense1 + sense1 ? freq sense2 ? sense2 + v fb2 i th2 tk/ss2 tk/ss1 pgood sw1 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sw2 tg2 sgnd i lim mode/pllin run1 run2 ltc3869 tg1
ltc3869/ltc3869-2 29 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion figure 12. branch current waveforms r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3869 f12 r sense2 v out2 c out2
ltc3869/ltc3869-2 30 38692fa for more information www.linear.com/ltc3869 reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. design example as a design example for a two channel high current regu- lator, assume v in = 12 v(nominal), v in = 20v(maximum), v out1 = 1.8 v, v out2 = 1.2 v, i max1,2 = 15 a, and f = 400khz (see figure 13). the regulated output voltages are determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? using 20k 1% resistors from both v fb nodes to ground, the top feedback resistors are ( to the nearest 1% standard value) 40.2k and 20k. the frequency is set by biasing the freq pin to 1v (see figure 9). the inductance values are based on a 35% maximum ripple current assumption (5.25 a for each channel). the highest value of ripple current occurs at the maximum input voltage: l = v out ? ? ?i l(max) 1 ? v out v in(max) ? ? ? ? ? ? ? ? channel 1 will require 0.78 h, and channel 2 will require 0.54h. the vishay ihlp4040dz-01, 0.56h inductor is chosen for both rails. at the nominal input voltage (12v), the ripple current will be: ?i l(nom) = v out ? ? l 1 ? v out v in(nom) ? ? ? ? ? ? ? ? channel 1 will have 6.8a (46%) ripple, and channel 2 will have 4.8a (32%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 18.4a for channel 1 and 17.4a for channel 2. the minimum on- time occurs on channel 2 at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) ? = 1.2v 20v(400khz) = 150ns with i lim floating, the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (43mv). r sense(equiv) = v sense(min) i load(max) + ?i l(nom) 2 the equivalent required r sense value is 2.4 m? for chan- nel 1 and 2.5 m? for channel 2. the dcr of the 0.56h inductor is 1.7 m? typical and 1.8 m? maximum for a 25c ambient. at 100 c, the estimated maximum dcr value is 2.3 m?. the maximum dcr value is just slightly under the equivalent r sense values. therefore, r2 is not required to divide down the signal. a pplica t ions i n f or m a t ion
ltc3869/ltc3869-2 31 38692fa for more information www.linear.com/ltc3869 a pplica t ions i n f or m a t ion figure 14. dcr sense efficiency vs r sense efficiency figure 13. high efficiency dual 400khz 1.8v/1.2v step-down converter load current (a) 0 85 efficiency (%) power loss (w) 90 161412108642 80 75 70 95 4 3 2 1 0 5 3869 f14 1.2v r sense 1.2v dcr sense 1.8v r sense 1.8v dcr sense v in = 12v mode = ccm dcr sense app: see figure 16 r sense app: see figure 19 efficiency power loss d3 d4 m1 m2 0.1f 40.2k 1% l1 0.56h 3.09k 1% 1nf 150pf 0.1f 0.1f 82f 25v c out1 330f 2 l1, l2: vishay ihlp4040dz-01, 0.56h m1, m3: renesas rjk0305dpb m2, m4: renesas rjk0330dpb 20k 1% 12.1k 1% v out1 1.8v 15a m3 m4 0.1f l2 0.56h 1nf 150pf c out2 330f 2 20k 1% 4.99k 1% 100k 1% v out2 1.2v 15a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + sense1 ? sense2 ? v fb1 v fb2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 4.5v to 20v 3869 f13 extv cc 0.1f 0.1f ltc3869 mode/pllin i lim run1 run2 3.09k 1% 4.7f 1f 2.2 + + 10f 25v 2 + 20k 1%
ltc3869/ltc3869-2 32 38692fa for more information www.linear.com/ltc3869 for a 2 m sense resistor, a short-circuit to ground will result in a folded back current of: i sc = 1/ 3 ( ) 50mv 0.002 C 1 2 90ns(20v) 0.56h ? ? ? ? ? ? = 6.7a a renesas rjk0330dpb, r ds(on) = 3.9 m?, is chosen for the bottom fet. the resulting power loss is: p sync = 20v C 1.8v 20v 15a ( ) 2 ? 1+ 0.005 ( ) ? 75 c C 25 c ( ) ? ? ? ? ? 0.0039 p sync = 1w c in is chosen for an rms current rating of at least 7.5 a at temperature assuming only channel 1 or 2 is on. c out is chosen with an equivalent esr of 4.5 m? for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.0045? ? 6.8a = 31mv pCp further reductions in output voltage ripple can be made by placing a 100f ceramic across c out . a pplica t ions i n f or m a t ion for each channel, 0.1f is selected for c1. r1 = l (dcr max at 25 c) ? c1 = 0.56h 1.8m ? 0.1f = 3.11k choose r1 = 3.09k the power loss in r1 at the maximum input voltage is: p loss r1 = (v in(max) ? v out ) ? v out r1 the resulting power loss for r1 is 11 mw for channel 1 and 7mw for channel 2. the sum of the sense resistor and dcr is 2.5m (max) for the r sense application whereas the inductor dcr for the dcr sense application is 1.8m ( max). as a result of the lower conduction losses from the switch node to v out , the dcr sensing application has higher efficiency. the power dissipation on the topside mosfet can be easily estimated. choosing a renesas rjk0305dpb mosfet results in: r ds(on) = 13m? ( max), v miller = 2.6v, c miller ? 150 pf. at maximum input voltage with t j (estimated) = 75c: p main = 1.8v 20v 15a ( ) 2 1 + (0.005)(75 c C 25 c) [ ] ? 0.013 ( ) + 20v ( ) 2 15a 2 ? ? ? ? ? ? 2 ( ) 150pf ( ) ? 1 5v C 2.6v + 1 2.6v ? ? ? ? ? ? 400khz ( ) = 329mw + 288mw = 617mw
ltc3869/ltc3869-2 33 38692fa for more information www.linear.com/ltc3869 typical a pplica t ions figure 15. 2.5v, 15a and 1.8v, 15a supply with dcr sensing, f sw = 350khz l1, l2: vishay ihlp5050ce-01, 0.68h c out1 , c out3 : murata grm32er60j107me20 c out2 , c out4 : kemet t520v337m004ate009 rntc1, rntc2: murata ncp18wf104j03rb 3869 f15 tg1 boost1 pgnd bg1 v in intv cc extv cc bg2 pgnd boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? 20k 0.1f 40.2k sense1 ? sense1 + run1 freq mode/pllin sw1 run2 i lim pgood pgood sw2 tg2 63.4k 86.6k 100k 20k 2.2 4.7f 0.1f 0.1f ltc3869 1nf 20k 0.1f 100pf 10f 2 82f 25v 2 1nf 15k 0.1f 100pf 0.1f cmdsh-3 m4 rjk0330dpb m3 rjk0305dpb m2 rjk0330dpb m1 rjk0305dpb cmdsh-3 0.1f l1 0.68h l2 0.68h 24.9k 24.9k 3.01k 3.01k v out2 1.8v 15a v in 4.5v to 20v v out1 2.5v 15a + c out1 100f 6.3v c out2 330f 4v 2 + c out3 100f 6.3v c out4 330f 4v 2 +
ltc3869/ltc3869-2 34 38692fa for more information www.linear.com/ltc3869 typical a pplica t ions figure 16. 1.8v, 15a and 1.2v, 15a supply, f sw = 400khz 3869 f16 tg1 boost1 pgnd bg1 v in intv cc extv cc bg2 pgnd boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? 20k 0.1f 20k sense1 ? sense1 + run1 freq mode/pllin sw1 run2 i lim pgood pgood sw2 tg2 63.4k 86.6k 100 100 100k 20k 2.2 4.7f 0.1f 0.1f ltc3869 1nf 18k 0.1f 150pf 10f 2 82f 25v 2 1.5nf 15k 0.1f 150pf 0.1f cmdsh-3 m4 rjk0330dpb m3 rjk0305dpb m2 rjk0330dpb m1 rjk0305dpb cmdsh-3 0.1f l2 0.4h v out2 1.2v 15a v in 4.5v to 20v v out1 1.8v 15a + c out1 100f 6.3v c out2 330f 4v 2 + c out3 100f 6.3v c out4 330f 4v 2 + l1, l2: vitec 59pr9875 c out1 , c out3 : murata grm31cr60j107me39l c out2 , c out4 : sanyo 2r5tpe330m9 100 100 0.002 l1 0.4h 0.002
ltc3869/ltc3869-2 35 38692fa for more information www.linear.com/ltc3869 typical a pplica t ions figure 17. high efficiency dual phase 1.2v, 40a supply, f sw = 250khz 3869 f17 tg1 boost1 pgnd bg1 v in intv cc extv cc bg2 pgnd boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? 0.1f sense1 ? sense1 + run1 freq mode/pllin sw1 run i lim pgood pgood sw2 tg2 86.6k 100 100 100k 20k 2.2 0.1f 4.7f 0.1f 0.1f ltc3869 10f 4 270f 16v 0.1f cmdsh-3 m4 rjk0330dpb m3 rjk0305dpb m2 rjk0330dpb 2 m1 rjk0305dpb cmdsh-3 0.1f l1 0.44h l2 0.44h 0.001 1% v out 1.2v 40a v in 4.5v to 14v + c out1 100f 6.3v 4 c out2 330f 2.5v 4 + 100 100 0.001 1% 2200pf 5.9k 100pf 20k l1, l2: pulse pa0513.441nlt c out1 : murata grm31cr60j107me39l c out2 : sanyo 2r5tpe330m9
ltc3869/ltc3869-2 36 38692fa for more information www.linear.com/ltc3869 figure 18. high efficiency dual phase 1.2v, 40a supply with dcr sensing, f sw = 250khz typical a pplica t ions 3869 f18 tg1 boost1 pgnd bg1 v in intv cc extv cc bg2 pgnd boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? 0.1f sense1 ? sense1 + run1 freq mode/pllin sw1 run i lim pgood pgood sw2 tg2 100k 20k 2.2 0.1f 4.7f 0.1f 0.1f ltc3869 10f 4 270f 16v 0.1f cmdsh-3 m4 rjk0330dpb 2 m3 rjk0305dpb m2 rjk0330dpb 2 m1 rjk0305dpb cmdsh-3 1f l1 0.47h l2 0.47h v out 1.2v 40a v in 4.5v to 14v + c out1 100f 6.3v 4 c out2 330f 2.5v 4 + 3300pf 10k 330pf 20k l1, l2: vishay ihlp5050fd-01, 0.47h c out1 : murata grm31cr60j107me39l c out2 : sanyo 2r5tpe330m9 3.92k 3.92k
ltc3869/ltc3869-2 37 38692fa for more information www.linear.com/ltc3869 typical a pplica t ions figure 19. small size, dual phase 0.9v, 50a supply, f sw = 400khz 3869 f19 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? 1nf sense1 ? sense1 + run1 freq mode/pllin sw1 run i lim pgood pgood sw2 tg2 100k 100 100 100k 10k 2.2 0.1f 4.7f 0.1f 0.1f ltc3869 10f 4 270f 16v 0.1f 400khz cmdsh-3 m4 rjk0330dpb 2 m3 rjk0305dpb 2 m2 rjk0330dpb 2 m1 rjk0305dpb 2 cmdsh-3 1f l1 0.23h l2 0.23h 0.001 1% v out 0.9v 50a v in 4.5v to 14v + c out1 100f 6.3v 2 c out2 330f 2.5v 4 + 100 100 0.001 1% 2700pf 5.1k 220pf 20k l1, l2: pulse pa0513.441nlt c out1 : murata grm31cr60j107me39l c out2 : sanyo 2r5tpe330m9
ltc3869/ltc3869-2 38 38692fa for more information www.linear.com/ltc3869 figure 20. 12v, 6a and 5v, 10a supply with dcr sensing, f sw = 250khz typical a pplica t ions 3869 f20 tg1 boost pgnd1 bg1 v in intv cc extv cc bg2 pgnd boost2 tk/ss1 i th1 v fb1 sgnd v fb2 i th2 tk/ss2 sense2 + sense2 ? 20k 0.1f 147k sense1 ? sense1 + run1 freq mode/pllin sw1 run2 i lim pgood pgood sw2 tg2 383k 100k 20k 2.2 4.7f 0.1f 0.1f ltc3869 5.6nf 10k 0.1f 47pf 4.7f 6 100f 50v 5.6nf 4.99k 0.1f 47pf 0.1f sdm10k45 m4 bsc093n040ls m3 bsc093n040ls m2 bsc093n040ls m1 bsc093n040ls sdm10k45 0.1f l1 13h l2 3.7h 24k 24k 18k 8.2k v out2 5v 10a v in 13v to 38v v out1 12v 6a + c out2 39f 16v 2 + c out2 39f 16v 2 + l1: wurth 7443551131 l2: wurth 7443551370 c out1 , c out2 : sanyo 16svpc39mv
ltc3869/ltc3869-2 39 38692fa for more information www.linear.com/ltc3869 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b)
ltc3869/ltc3869-2 40 38692fa for more information www.linear.com/ltc3869 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. .386 ? .393* (9.804 ? 9.982) gn28 rev b 0212 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 202122232425262728 19 18 17 13 14 16 15 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4. pin 1 can be bevel edge or a dimple gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b)
ltc3869/ltc3869-2 41 38692fa for more information www.linear.com/ltc3869 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 04/13 revised schematics 35-38 updated package drawings 39-40
ltc3869/ltc3869-2 42 38692fa for more information www.linear.com/ltc3869 ? linear technology corporation 2011 lt 0413 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3869 r ela t e d p ar t s typical a pplica t ion 3.3v/5a, 5v/5a converter using sense resistors 0.1f 90.9k 1% l2 2.2h 1000pf 1000pf 1000pf 22f 50v 20k 1% 10k 1% v out1 3.3v 5a 0.1f 147k 1% l2 3.3h 1000pf c out2 150f 20k 1% 15k 1% 122k 1% v out2 5v 5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + run2 extv cc sense1 ? sense2 ? v fb1 v fb2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 7v to 24v 3869 ta02 0.1f 100pf 0.1f ltc3869 mode/pllin i lim run1 4.7f + c out1 220f + 10pf 15pf 100pf 10 10 10 10 2.2 1f d4 d3 l1: tdk rlf 7030t-2r2m5r4 l2: tdk ulf10045t-3r3n6r9 c out1 : sanyo 4tpe220mf c out2 : sanyo 6tpe150mi 8m 8m m1 m2 si4816bdy si4816bdy part number description comments ltc3850/ ltc3850-1/ ltc3850-2 dual 2-phase, high efficiency synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 780khz frequency, 4v v in 30v, 0.8v v out 5.25v ltc3861/ ltc3861-1 dual, multiphase, synchronous step-down dc/dc controller with differential amplifier(s) and tr i -state output drive operates with power blocks, drmos devices or external drivers/ mosfets, 3v v in 24v ltc3855 dual, multiphase, synchronous step-down dc/dc controller with differential amplifier and dcr temperature compensation phase-lockable fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12v ltc3890 dual, high v in low i q synchronous step-down dc/dc controller pll capable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3856 2-phase, single output synchronous step-down dc/dc controller with differential amplifier and dcr temperature compensation phase-lockable fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.8v v out 5v ltc3853 triple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 750khz frequency, 4v v in 24v, v out3 up to 13.5v ltc3851a/ ltc3851a-1 no r sense ? wide v in range synchronous step-down dc/dc controller pll fixed frequency 250khz to 750khz, 4v v in 38v, 0.8v v out 5.25v, msop-16e, 3mm 3mm qfn-16, ssop-16 ltc3833 fast controlled on-time, high frequency synchronous step-down controller with differential amplifier up to 2mhz operating frequency, 4v v in 38v, 0.8v v out 5.5v, 3mm 4mm qfn-20, tssop-20e

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